1. Field of the Invention
The invention relates to an interruption signal generating apparatus for generating an interruption signal which is used in a computer system.
2. Related Art
A computer system has an interruption signal generating apparatus for generating a signal (hereinafter, referred to as an xe2x80x9cinterruption signalxe2x80x9d) for requesting an interrupting process to a CPU (Central Processing Unit) for allowing the CPU to execute a predetermined interrupting process every predetermined time that is, periodically. The computer system switches an operation mode, for instance, between a normal mode and a stop mode in order to reduce an electric power consumption.
In the normal mode, a clock (hereinafter, referred to as a xe2x80x9cbus clockxe2x80x9d) for synchronously performing a process to be executed in the whole computer system is generated in the computer system and the bus clock is supplied to each operating section of the system. Therefore, in the normal mode, the conventional interruption signal generating apparatus generates the interruption signal synchronously with the bus clock.
In the stop mode, however, since there is no process to be executed, the supply of the bus clock is stopped. Therefore, in the stop mode, the conventional interruption signal generating apparatus cannot generate the interruption signal. That is, the conventional interruption signal generating apparatus has a problem such that it cannot generate the interruption signal irrespective of the operation mode.
The invention is made to solve the above problem and it is an object of the invention to provide an interruption signal generating apparatus which can generate an interruption signal irrespective of an operation mode.
To accomplish the above object, according to a first aspect of the invention, there is provided an interruption signal generating apparatus used for a computer system that receives a first clock and a second clock from the computer system and outputs an interruption signal for requesting an execution of an interrupting process at a time interval corresponding to a frequency obtained by dividing in frequency the second clock, wherein the first clock is provided according to an operation mode of the computer system, and the second clock has a period longer than that of the first clock, is used to generate the interruption signal, and is provided irrespective of the operation mode of the computer system, the interruption signal generating apparatus comprising: a counter unit that counts the time interval based upon the second clock and outputs a count-up signal indicating an end of the counting; a first generating unit that detects the end of the counting indicated by the count-up signal while the first clock is being provided and generates a first interruption signal indicating the detection according to the first clock; a second generating unit that detects the end of the counting indicated by the count-up signal while the first clock is not being provided and generates a second interruption signal indicating the detection according to the second clock; and a selecting unit that selectively outputs the first interruption signal and the second interruption signal according to the operation mode of the computer system.
It is desirable that the first clock is a bus clock signal for synchronizing the operation of the computer system as a whole.
It is desirable that the count-up signal indicates the end of the counting by a change in edge of the count-up signal, the first generating unit has a first differentiating circuit that detects the edge, and the second generating unit has a second differentiating circuit that detects the edge. It is further desirable that the first and second generating units are supplied with a permission signal for permitting an output of the first and second interruption signals by the computer system, the first generating unit further has a first holding circuit that holds a first detection signal indicative of the detection of the edge in response to the detection of the edge by the first differentiating circuit, the second generating unit further has a second holding circuit that holds a second detection signal indicative of the detection of the edge in response to the detection of the edge by the second differentiating circuit, the first generating unit generates the first interruption signal in accordance with the first clock, the first detection signal, and the permission signal, and the second generating unit generates the second interruption signal in accordance with the second clock, the second detection signal, and the permission signal.
It is desirable that the computer system restarts the supply of the first clock to the first generating unit of the interruption signal generating apparatus in response to the second interruption signal which is outputted from the selecting unit, and the second generating unit has a reset circuit that resets the second interruption signal in response to the restart of the supply of the first clock.
It is desirable that said signal selected by said selecting unit is outputted at substantially the same time with said output of said count-up signal indicative of said end of said counting of said time interval. It is more desirable that a time interval between adjacent ones of a plurality of first interruption signals during a provision of the first clock, a time interval between adjacent ones of a plurality of second interruption signals during an unprovision of the first clock, a time interval between last one of a plurality of first interruption signals during a provision of the first clock and first one of the plurality of second interruption signals during an unprovision of the first clock following the provision of the first clock, and a time interval between last one of a plurality of second interruption signals during a unprovision of the first clock and a first one of a plurality of first interruption signals during a provision of the first clock following the unprovision of the first clock are substantially identical with each other.
According to a second aspect of the present invention, there is provided a computer system comprising: an interruption signal generating apparatus specified according to the first aspect of the present invention; a central processing unit that stops the supply of the first clock in accordance with a predetermined program while the first clock is being supplied; and a system controller that starts the supply of the first clock in response to the interruption signal from the interruption signal generating apparatus while the first clock is being unprovided.